1 Standard library

     2 ================

     3 

     4 ..

     5     Documentation originally part of Smarteh's user Manual, and donated to Beremiz project.

     6 

     7 

     8 .. list-table::

     9 

    10     * - .. figure:: library_panel.png

    11 

    12             Library browser

    13 

    14       - Library contains various groups of standard

    15         and user defined functions. They support the

    16         usage in different programmable controller

    17         programming languages inside POUs.

    18 

    19 

    20     * - .. figure:: block_properties.png

    21 

    22             Block Properties

    23 

    24       - Block Properties pop-up window can be

    25         opened by double-click on function block.

    26         Some of the blocks can have more inputs than

    27         default. This is selectable in the Inputs field

    28         (e.g. ADD block). Also an Execution Order of

    29         the blocks can be programmer-defined. All

    30         blocks have an additional Execution Control

    31         check-box. If it is checked than two new pins

    32         are added (EN – input and ENO – output) to

    33         control dynamically their execution.

    34 

    35 

    36 Standard function blocks

    37 ------------------------

    38 

    39 .. highlight:: text

    40 

    41 .. list-table::

    42 

    43     * - .. figure:: std_block-012.png

    44 

    45             SR bistable

    46 

    47       - The SR bistable is a latch where the Set dominates.::

    48 

    49             ( BOOL:S1, BOOL:R ) => ( BOOL:Q1 )

    50 

    51         This function represents a standard set-dominant set/reset flip

    52         flop. The Q1 output become TRUE when the input S1 is TRUE and

    53         the R input is FALSE. In the same way, the Q1 output become

    54         FALSE when the input S1 is FALSE and the R input is TRUE. After

    55         one of these transitions, when both the S1 and R signals return to

    56         FALSE, the Q1 output keeps the previous state until a new

    57         condition occurs. If you apply a TRUE condition for both the

    58         signals, the Q1 output is forced to TRUE (set-dominant).

    59 

    60 

    61     * - .. figure:: std_block-010.png

    62 

    63             RS bistable

    64 

    65       - The RS bistable is a latch where the Reset dominates.::

    66 

    67             ( BOOL:S, BOOL:R1 ) => ( BOOL:Q1 )

    68 

    69         This function represents a standard reset-dominant set/reset flip

    70         flop. The Q1 output become TRUE when the input S is TRUE and

    71         the R1 input is FALSE. In the same way, the Q1 output become

    72         FALSE when the input S is FALSE and the R1 input is TRUE. After

    73         one of these transitions, when both the S and R1 signals return to

    74         FALSE, the Q1 output keeps the previous state until a new

    75         condition occurs. If you apply a TRUE condition for both the

    76         signals, the Q1 output is forced to FALSE (reset-dominant).

    77 

    78 

    79     * - .. figure:: std_block-019.png

    80 

    81             SEMA Semaphore

    82 

    83       - The semaphore provides a mechanism to allow software elements

    84         mutually exclusive access to certain resources.::

    85 

    86             ( BOOL:CLAIM, BOOL:RELEASE ) => ( BOOL:BUSY )

    87 

    88         This function block implements a semaphore function. Normally

    89         this function is used to synchronize events. The BUSY output is

    90         activated by a TRUE condition on the CLAIM input and it is de-

    91         activated by a TRUE condition on the RELEASE input.

    92 

    93 

    94     * - .. figure:: std_block-021.png

    95 

    96             R_TRIG Rising edge detector

    97 

    98       - The output produces a single pulse when a rising edge is detected.::

    99 

   100             ( BOOL:CLK ) => ( BOOL:Q )

   101 

   102         This function is a rising-edge detector. The Q output becomes

   103         TRUE when a 0 to 1 (or FALSE to TRUE or OFF to ON) condition is

   104         detected on the CLK input and it sustains this state for a complete

   105         scan cycle.

   106 

   107 

   108     * - .. figure:: std_block-023.png

   109 

   110             F TRIG

   111 

   112       - Falling edge detector

   113         The output Q produces a single pulse when a falling edge is

   114         detected.::

   115 

   116             ( BOOL:CLK ) => ( BOOL:Q )

   117 

   118         This function is a falling-edge detector. The Q output becomes

   119         TRUE when a 1 to 0 (or TRUE to FALSE or ON to OFF) condition is

   120         detected on the CLK input and it sustains this state for a complete

   121         scan cycle.

   122 

   123 

   124     * - .. figure:: std_block-030.png

   125 

   126             CTU

   127             CTU_DINT,

   128             CTU_LINT,

   129             CTU_UDINT, CTU_ULINT

   130             Up-counter

   131 

   132       - The up-counter can be used to signal when a count has reached a

   133         maximum value.::

   134 

   135             CTU:       ( BOOL:CU, BOOL:R, INT:PV ) => ( BOOL:Q, INT:CV )

   136             CTU_DINT:  ( BOOL:CU, BOOL:R, DINT:PV ) => ( BOOL:Q, DINT:CV )

   137             CTU_LINT:

   138             ( BOOL:CU, BOOL:R, LINT:PV ) => ( BOOL:Q, LINT:CV )

   139             CTU_UDINT: ( BOOL:CU, BOOL:R, UDINT:PV ) => ( BOOL:Q, UDINT:CV )

   140             CTU_ULINT: ( BOOL:CU, BOOL:R, ULINT:PV ) => ( BOOL:Q, ULINT:CV )

   141 

   142         The CTU function represents an up-counter. A rising-edge on CU

   143         input will increment the counter by one. When the programmed

   144         value, applied to the input PV, is reached, the Q output becomes

   145         TRUE. Applying a TRUE signal on R input will reset the counter to

   146         zero (Asynchronous reset). The CV output reports the current

   147         counting value.

   148 

   149 

   150     * - .. figure:: std_block-028.png

   151 

   152             CTD

   153             CTD_DINT, CTD_LINT,

   154             CTD_UDINT, CTD_ULINT

   155             Down-counter

   156 

   157       - The down-counter can be used to signal when a count has reached

   158         zero, on counting down from a pre-set value.::

   159 

   160             CTD:       ( BOOL:CD, BOOL:LD, INT:PV ) => ( BOOL:Q, INT:CV )

   161             CTD_DINT:  ( BOOL:CD, BOOL:LD, DINT:PV ) => ( BOOL:Q, DINT:CV )

   162             CTD_LINT:  ( BOOL:CD, BOOL:LD, LINT:PV ) => ( BOOL:Q, LINT:CV )

   163             CTD_UDINT: ( BOOL:CD, BOOL:LD, UDINT:PV ) => ( BOOL:Q, UDINT:CV )

   164             CTD_ULINT: ( BOOL:CD, BOOL:LD, ULINT:PV ) => ( BOOL:Q, ULINT:CV )

   165 

   166         The CTD function represents a down-counter. A rising-edge on CD

   167         input will decrement the counter by one. The Q output becomes

   168         TRUE when the current counting value is equal or less than zero.

   169         Applying a TRUE signal on LD (LOAD) input will load the counter

   170         with the value present at input PV (Asynchronous load). The CV

   171         output reports the current counting value.

   172 

   173 

   174     * - .. figure:: std_block-035.png

   175 

   176             CTUD

   177             CTUD_DINT,

   178             CTUD_LINT,

   179             CTUD_UDINT,

   180             CTUD_ULINT

   181             Up-down counter

   182 

   183       - The up-down counter has two inputs CU and CD. It can be used to

   184         both count up on one input and down on the other.::

   185 

   186             CTUD:       ( BOOL:CU, BOOL:CD, BOOL:R, BOOL:LD, INT:PV ) => ( BOOL:QU, BOOL:QD, INT:CV )

   187             CTUD_DINT:  ( BOOL:CU, BOOL:CD, BOOL:R, BOOL:LD, DINT:PV ) => ( BOOL:QU, BOOL:QD, DINT:CV )

   188             CTUD_LINT:  ( BOOL:CU, BOOL:CD, BOOL:R, BOOL:LD, LINT:PV ) => ( BOOL:QU, BOOL:QD, LINT:CV )

   189             CTUD_UDINT: ( BOOL:CU, BOOL:CD, BOOL:R, BOOL:LD, UDINT:PV ) => ( BOOL:QU, BOOL:QD, UDINT:CV )

   190             CTUD_ULINT: ( BOOL:CU, BOOL:CD, BOOL:R, BOOL:LD, ULINT:PV ) => ( BOOL:QU, BOOL:QD, ULINT:CV )

   191         

   192         This function represents an up-down programmable counter. A

   193         rising-edge on the CU (COUNT-UP) input increments the counter

   194         by one while a rising-edge on the CD (COUNT-DOWN) decreases

   195         the current value. Applying a TRUE signal on R input will reset the

   196         counter to zero. A TRUE condition on the LD signal will load the

   197         counter with the value applied to the input PV (PROGRAMMED

   198         VALUE). QU output becomes active when the current counting

   199         value is greater or equal to the programmed value. The QD output

   200         becomes active when the current value is less or equal to zero.

   201         The CV output reports the current counter value.

   202 

   203 

   204     * - .. figure:: std_block-037.png

   205 

   206             TP

   207             Pulse timer

   208 

   209       - The pulse timer can be used to generate output pulses of a given

   210         time duration.::

   211 

   212             ( BOOL:IN, TIME:PT ) => ( BOOL:Q, TIME:ET )

   213 

   214         This kind of timer has the same behaviour of a single-shot timer or

   215         a monostable timer.

   216         When a rising-edge transition is detected on the IN input, the Q

   217         output becomes TRUE immediately. This condition continues until

   218         the programmed time PT, applied to the relative pin, is elapsed.

   219         After that the PT is elapsed, the Q output keeps the ON state if

   220         the input IN is still asserted else the Q output returns to the OFF

   221         state. This timer is not re-triggerable. This means that after that

   222         the timer has started it can't be stopped until the complete

   223         session ends. The ET output reports the current elapsed time.

   224 

   225 

   226     * - .. figure:: std_block-042.png

   227 

   228             TON

   229             On-delay timer

   230                     

   231       - The on-delay timer can be used to delay setting an output true,

   232         for fixed period after an input becomes true.::

   233 

   234             ( BOOL:IN, TIME:PT ) => ( BOOL:Q, TIME:ET )

   235 

   236         Asserting the input signal IN of this function starts the timer.

   237         When the programmed time, applied to the input PT, is elapsed

   238         and the input IN is still asserted, the Q output becomes TRUE. This

   239         condition will continue until the input IN is released. If the IN

   240         input is released before time elapsing, the timer will be cleared.

   241         The ET output reports the current elapsed time.

   242 

   243 

   244     * - .. figure:: std_block-044.png

   245 

   246             TOF

   247             Off-delay timer

   248 

   249       - The off-delay timer can be used to delay setting an output false,

   250         for fixed period after input goes false.::

   251 

   252         ( BOOL:IN, TIME:PT ) => ( BOOL:Q, TIME:ET )

   253 

   254         Asserting the input signal IN of this function immediately activates

   255         the Q output. At this point, releasing the input IN will start the

   256         time elapsing. When the programmed time, applied to the input

   257         PT, is elapsed and the input IN is still released, the Q output

   258         becomes FALSE. This condition will be kept until the input IN is

   259         released. If the IN input is asserted again before time elapses, the

   260         timer will be cleared and the Q output remains TRUE. The ET

   261         output reports the current elapsed time.

   262 

   263 

   264 Additional function blocks

   265 --------------------------

   266 

   267 

   268 .. list-table::

   269 

   270     * - .. figure:: std_block-055.png

   271     

   272             RTC

   273             Real Time Clock

   274 

   275       - The RTC function block sets the output CDT to the input value PDT at the next

   276         evaluation of the function block following a transition from 0 to 1 of the IN input. The CDT output

   277         of the RTC function block is undefined when the value of IN is 0.

   278 

   279         .. line-block:: 

   280 

   281             PDT = Preset date and time, loaded on rising edge of IN

   282             CDT = Current date and time, valid when IN=1

   283             Q = copy of EN

   284 

   285         .. code-block:: 

   286 

   287             (BOOL:IN, PDT:DT) => (BOOL:Q, CDT:DT)

   288 

   289 

   290     * - .. figure:: std_block-049.png

   291     

   292             INTEGRAL

   293             Integral

   294 

   295       - The integral function block integrates the value of input XIN over

   296         time.::

   297 

   298             ( BOOL:RUN, BOOL:R1, REAL:XIN, REAL:X0, TIME:CYCLE ) => ( BOOL:Q, REAL:XOUT )

   299 

   300         When input RUN is True and override R1 is False, XOUT will

   301         change for XIN value depends on CYCLE time value sampling

   302         period. When RUN is False and override R1 is True, XOUT will hold

   303         the last output value. If R1 is True, XOUT will be set to the X0

   304         value.::

   305 

   306             XOUT = XOUT + (XIN * CYCLE)

   307 

   308 

   309     * - .. figure:: std_block-051.png

   310     

   311             DERIVATIVE

   312             Derivative

   313 

   314       - The derivative function block produces an output XOUT

   315         proportional to the rate of change of the input XIN.::

   316 

   317             ( BOOL:RUN, REAL:XIN, TIME:CYCLE ) => ( REAL:XOUT )

   318 

   319         When RUN is True, XOUT will change proportional to the rate of

   320         changing of the value XIN depends on CYCLE time value sampling

   321         period.::

   322 

   323             XOUT = ((3 * (XIN - XIN(to-3))) + XIN(to-1) – XIN(to-2) ) / (10 * CYCLE)

   324 

   325 

   326     * - .. figure:: std_block-060.png

   327     

   328             PID

   329             Proportional, Integral, Derivative

   330 

   331       - The PID (Proportional, Integral, Derivative) function block

   332         provides the classical three term controller for closed loop

   333         control. It does not contain any output limitation parameters

   334         (dead-band, minimum, maximum, …) or other parameters

   335         normally used for real process control (see also PID_A).::

   336 

   337             ( BOOL:AUTO, REAL:PV, REAL:SP, REAL:X0, REAL:KP, REAL:TR, REAL:TD, TIME:CYCLE ) => ( REAL:XOUT )

   338 

   339         When AUTO is False, PID function block XOUT will follow X0 value.

   340         When AUTO is True, XOUT will be calculated from error value (PV

   341         process variable – SP set point), KP proportional constant, TR

   342         reset time, TD derivative constant and CYCLE time value sampling

   343         period.::

   344 

   345             XOUT = KP * ((PV-SP) + (I_OUT/TR) + (D_OUT * TD))

   346 

   347 

   348     * - .. figure:: std_block-062.png

   349     

   350             RAMP

   351             Ramp

   352 

   353       - The RAMP function block is modelled on example given in the

   354         standard but with the addition of a 'Holdback' feature.::

   355 

   356             ( BOOL:RUN, REAL:X0, REAL:X1, TIME:TR, TIME:CYCLE, BOOL:HOLDBACK, REAL:ERROR, REAL:PV ) => ( BOOL:RAMP, REAL:XOUT )

   357 

   358         When RUN and HOLDBACK are False, XOUT will follow X0 value.

   359         When RUN is True and HOLDBACK value is False, XOUT will change

   360         for ``OUT(to-1) + (X1 – XOUT(to-1))`` every CYCLE time value sampling

   361         period.

   362 

   363 

   364     * - .. figure:: std_block-064.png

   365     

   366             HYSTERESIS

   367             Hysteresis

   368 

   369       - The hysteresis function block provides a hysteresis boolean output

   370         driven by the difference of two floating point (REAL) inputs XIN1

   371         and XIN2.::

   372 

   373             ( REAL:XIN1, REAL:XIN2, REAL:EPS ) => ( BOOL:Q )

   374 

   375         When XIN1 value will be grater than XIN2 + EPS value, Q becomes

   376         True. When XIN1 value will be less than XIN2 - EPS value, Q

   377         becomes False.